The present invention pertains to the field of digital data transfer, and, more particularly, to an apparatus for and method of facilitating proper data transfer between two or more digital memory elements such as, for example, registers.
FIGS. 1(a) through 1(c) illustrate the process of data transfer in a conventional system. FIG. 1(a) illustrates a first register 10 which receives both data and a clock signal. The arrangement of FIG. 1(a) also includes a second register 20 which is supposed to receive data from the first register 10. The output of the first data register 10 is labelled Q1 and the output of second data register 20 is labelled Q2. Propagation delays are represented as two functional blocks. The first functional block, labelled TD.sub.DATA, represents the data propagation delay. The second functional block, labelled TD.sub.CLK, represents the clock delay. The "clock to Q2 delay plus the data setup time" and the "register's internal clock delay" are aggregated into TD.sub.DATA and TD.sub.CLK, respectively.
The timing diagrams illustrated in FIG. 1(b) represent proper data transfer through the first and second registers 10 and 20. The signal "CLOCK" serves as a common causal signal. As can be seen in FIG. 1(b), the data makes a transition from a low state to a high state in the Nth clock cycle. The output Q1 of first data register 10 accordingly makes the transition from a low state to a high state in clock cycle N+1. The output of second register 20, Q2, makes a transition from a low state to a high state in clock cycle N+2. Thus, in the situation depicted, there is an orderly transfer of data through the first register 10 to the second register 20. This proper operation is possible because the clock time or propagation delay TD.sub.CLOCK does not exceed the data time or propagation delay TD.sub.DATA.
The timing diagram illustrated in FIG. 1(c) shows the problem resulting when the common causal signal ("CLOCK") experiences a greater time delay than does the data (TD.sub.CLK &gt;TD.sub.DATA). Notice that the data of Q2 becomes a logic level "1" during cycle N+1, i.e., the second register 20 is updated with the same data as the first register 10 within the same cycle of the causal signal. Unless the first register 10 and/or the data path delay can "hold" the data long enough after the second register 20 receives CLOCK, the receiver's realization of the causal edge after the sender will cause transmission failure. This problem is more difficult to solve when the data wire is bidirectional because then the designer cannot simply input the causal signal initially to the receiver device and allow it to propagate to the sender later.
Prior practices for guaranteeing successful data transmission include providing a very high speed clock which times sequencing logic to guarantee a minimum delay between when a chip may acquire data and when it may update, employing a phase locked loop, and designing an analog delay into the enable path of the driver. Each approach has disadvantages. For example, the first approach requires a higher clock rate than that otherwise required for proper system operation. The phase locked loops required in the second approach lock to certain frequency ranges; frequencies outside of those ranges will cause spurious operation. The main disadvantage of the second approach, however, is that a minimum frequency is required. Also, the second approach is complicated and represents a significant testability problem. The third approach may be a good solution if a wide enough range of time can be specified between the minimum delay an output must hold the data and the maximum delay from the causal signal edge until the data must be valid. If this is not the case, which is very often the situation because of semiconductor process and temperature variations, the third approach is not viable.
There is thus a need for an arrangement for facilitating successful data transmission between two devices such as registers. There is a need for such an arrangement method which guarantees successful data transmission without requiring a higher clock speed or utilizing a phase locked loop. There is also still need for an approach which is not sensitive to the range of time specified between the minimum delay an output must hold data and the maximum delay from a causal signal edge until the data must be valid.